This web page takes a better look at the Raspberry Pi memory hierarchy. Every level of the memory hierarchy has a capacity and speed. Capacities are relatively easy to discover by querying the working system or reading the ARM1176 technical reference guide. Pace, nonetheless, will not be as straightforward to discover and should usually be measured. I take advantage of a simple pointer chasing approach to characterize the behavior of every degree within the hierarchy. The technique also reveals the behavior of memory-associated performance counter occasions at each degree. The Raspberry Pi implements five levels in its memory hierarchy. The levels are summarized in the table beneath. The very best level consists of virtual memory pages that are maintained in secondary storage. Raspbian Wheezy retains its swap space in the file /var/swap on the SDHC card. That is sufficient house for 25,600 4KB pages. You might be allowed as many pages as will match into the preallocated swap house.

The Raspberry Pi has both 256MB (Model A) or 512MB (Mannequin B) of primary memory. This is enough house for 65,536 pages or 131,072 physical pages, if all of primary memory have been available for paging. It isn’t all accessible for person-space programs because the Linux kernel wants space for its personal code and information. Linux also helps massive pages, but that’s a separate subject for now. The vmstat command displays details about virtual memory utilization. Please refer to the man web page for utilization. Vmstat is an efficient device for troubleshooting paging-associated efficiency points because it shows page in and out statistics. The processor within the Raspberry Pi is the Broadcom BCM2835. The BCM2835 does have a unified level 2 (L2) cache. Nevertheless, the L2 cache is dedicated to the VideoCore GPU. Memory references from the CPU aspect are routed across the L2 cache. The BCM2835 has two level 1 (L1) caches: a 16KB instruction cache and a 16KB knowledge cache.

Our analysis below concentrates on the info cache. The info cache is 4-means set associative. Each approach in an associative set shops a 32-byte cache line. The cache can handle as much as four active references to the same set with out battle. If all four methods in a set are legitimate and a fifth reference is made to the set, then a battle occurs and one of the 4 ways is victimized to make room for the brand new reference. The info cache is nearly indexed and physically tagged. Cache strains and tags are stored individually in DATARAM and TAGRAM, respectively. Virtual tackle bits 11:5 index the TAGRAM and DATARAM. Given a 16KB capacity, 32 byte lines and four ways, there must be 128 units. Virtual handle bits 4:Zero are the offset into the cache line. The info MicroTLB interprets a digital address to a bodily handle and sends the physical address to the L1 knowledge cache.

The L1 information cache compares the bodily tackle with the tag and MemoryWave Official determines hit/miss status and the proper means. The load-to-use latency is three (3) cycles for an L1 information cache hit. The BCM2835 implements a two level translation lookaside buffer (TLB) construction for MemoryWave Official virtual to physical address translation. There are two MicroTLBs: a ten entry information MicroTLB and Memory Wave a ten entry instruction MicroTLB. The MicroTLBs are backed by the main TLB (i.e., the second stage TLB). The MicroTLBs are fully associative. Every MicroTLB translates a virtual address to a physical address in one cycle when the page mapping information is resident within the MicroTLB (that is, successful in the MicroTLB). The principle TLB is a unified TLB that handles misses from the instruction and information MicroTLBs. A 64-entry, 2-manner associative construction. Major TLB misses are dealt with by a hardware web page table walker. A web page table walk requires not less than one additional memory entry to find the page mapping data in major Memory Wave memory.