It ought to have been noted within the textual content that much of the description of multi-cache interaction is particular to x86 and similarly “sequentially-constant” architectures. Most modern architectures aren’t sequentially constant, and threaded packages should be extraordinarily cautious about one thread relying on knowledge written by another thread changing into visible in the order in which it was written. Alpha, PPC, Itanium, and (sometimes) SPARC, but not x86, AMD, or MIPS. The consequence of the requirement to maintain sequential consistency is poor performance and/or horrifyingly complex cache interaction equipment on machines with more than (about) 4 CPUs, so we can expect to see extra non-x86 multi-core chips in use quickly. I believe your criticism is misdirected. The textual content would not touch on memory consistency at all - it’s totally out of its scope. Besides, you need a cache coherency protocol on any multi processor system. As regards to memory consistency, there are totally different opinions.

A while in the past there was a really interesting dialogue in RealWorldTech where Linus Torvalds made an interesting point that it can be argued that explicit memory obstacles are costlier than what the CPU has to do in an effort to create the illusion of sequential memory consistency, because express MBs are by necessity more common and even have stronger guarantees. Sorry, not true. It describes how caches of various x86 CPUs interact, but does not say it only describes x86, falsely suggesting that’s how each different machine does it too. It leaves the affordable reader beneath the impression that programmers don’t need to know anything about memory consistency. That’s not completely true even on x86, but is simply false on most non-x86 platforms. If Ulrich is writing for people programming solely x86, the article ought to say so without quibbling. If not, it ought to name out places where it is describing x86-specific behavior. To the better of my knowledge, the outline in the article applies to all cache coherent techniques, together with those listed in your previous put up.

It has nothing to do with memory consistency, which is a matter principally inside to the CPU. I am very probably mistaken, of course - I am not a hardware system designer - so I’m glad to discuss it. Can you describe how the cache/Memory Wave Protocol habits in an Alpha (for instance